| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which can perform data read and data write operations in accordance with various address allocations and keep its circuit area and wiring region reduced respectively. SOLUTION: In each of memory sections ME<SB>0</SB>-ME<SB>h-1</SB>, in accordance with a control signal from a column decoder 4, each column gate CG<SB>0</SB>-CG<SB>m-1</SB>connects corresponding pairs of bit lines BL<SB>0</SB>, BL<SB>0</SB>B-BL<SB>m-1</SB>, BL<SB>m-1</SB>B with a first sense amplifier 12 and a first write buffer 13 via pairs of data lines ZD<SB>0</SB>, ZD<SB>0</SB>B-ZD<SB>h-1</SB>, ZD<SB>h-1</SB>B when an access is performed by the Zbit and connects corresponding pairs of bit lines BL<SB>0</SB>, BL<SB>0</SB>B-BL<SB>m-1</SB>, BL<SB>m-1</SB>B with a second sense amplifier 14 and a second write buffer 15 via pairs of data lines YD<SB>0</SB>, YD<SB>0</SB>B-YD<SB>h-1</SB>, YD<SB>h-1</SB>B when an access is performed by the Ybit. COPYRIGHT: (C)2008,JPO&INPIT
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