| 摘要 |
An SRAM cell which uses a fin-type transistor, and wherein degradation in the access performance is able to be suppressed by reducing the parasitic capacitance of a bit line. An SRAM cell is configured using transistors (PU1, PU2, PD1, PD2, PG1, PG2) having fin structures and a thin-film local metal wiring layer (M0). Bit lines (BL, NBL) are formed in the local metal wiring layer (M0), and diffusion layer contacts (2g, 2h) corresponding to bit line nodes are connected to the bit lines (BL, NBL) through vias (5a, 5b). |
