Method, device and system for aggregation of shared address devices

摘要

Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space.

主权项

1. A device for operation in a computer platform, the device comprising:
a first interface to couple the device to a host bus of the computer platform, the host bus to provide communications referencing a shared address space, wherein the first interface to couple the device via the host bus to a first input/output (I/O) device; an aggregation control unit including circuit logic to receive resource information generated by a pre-boot software process of the computer platform, wherein the resource information is to identify the first I/O device as a child device of the device, wherein, based on the first I/O device being identified by the resource information as the child device, the aggregation control unit to represent a first resource in the first I/O device to a host operating system (OS) of the computer platform as a resource that resides in the device, including the aggregation control unit to represent a first address in the shared address space to the host OS as addressing the first resource, wherein memory map information is to identify the first address to the host OS as an address of the device, and wherein a communication of enumeration information is to be blocked to prevent an identification of the first I/O device, by the host OS, as a physical device that is distinct from the device; and a second interface to provide communications between the aggregation control unit and a processor core executing the host OS.