| 摘要 |
PURPOSE:To provide a memory access controller with which error detected data can be synchronously reloaded into proper data without affecting the throughput of a CPU and the speed of access to a memory is not degraded. CONSTITUTION:A memory control means 1 controls a memory 7 and a data path control part 3, and the data path control part 3 controls a WR data path 4 and an RD data path 5. The WR data path 4 writes data from a bus 6, adds an error code to those data and outputs them to a memory 7. The RD data path 5 reads data from the memory 7, detects the error of those data, corrects them and outputs them to the bus 6 and the WR data path 4. Thus, when any error is detected in the data from the memory 7, with this invention, the error is corrected within one bus cycle of the CPU and the relevant data in the memory 7 can be properly reloaded. Therefore, it can be assured that the data in the memory 7 become a proper value at all times. |
