| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital noise eliminator applicable for a high-speed interface and capable of outputting a normal output signal even during a transient state. <P>SOLUTION: A digital noise eliminator 100 includes a shift register constituted of FF1(1)-1(n) (n is an integer of 6 or more); match decision circuits M1(1)-M1(m) (m is an integer of 3 or more) respectively connected to three FFs out of FF1(1)-1(n), for deciding a match of logical values of the output signals output from the above three FFs; and a majority circuit V1 connected to the match decision circuits M1(1)-M1(m), for deciding majority of the logical values of the respective output signals from the match decision circuits M1(1)-M1(m). <P>COPYRIGHT: (C)2005,JPO&NCIPI |
