Solid-state imaging device

摘要

A vertical shift register section includes M logic circuits for outputting row selection control signals respectively to M row selection wiring lines and shift register circuits disposed for every two row selection wiring lines. The M logic circuits, when a binning control signal Vbin1 or Vbin2 and an output signal of the shift register circuit both have significant values, output a row selection control signal Vsel so as to close a readout switch. The vertical shift register section, by controlling the timing at which the binning control signals Vbin1 and Vbin2 take significant values, realizes a normal operation mode for successively selecting the two row selection wiring lines and a binning operation mode for simultaneously selecting the two row selection wiring lines. Accordingly, a vertical binning operation is realized by a small vertical shift register.

主权项

1. A solid-state imaging device comprising:
a photodetecting section having M×N (M is an even number not less than 2, N is an integer not less than 2) pixels each including a photodiode and a readout switch connected at one end to the photodiode that are arrayed two-dimensionally in M rows and N columns; M row selection wiring lines arranged for each row, and connected to control terminals of the readout switches included in the pixels of corresponding rows; N readout wiring lines connected to the other ends of the readout switches included in the pixels of corresponding columns and reading out charges from the photodiodes; and a vertical shift register section for providing row selection control signals for controlling opening and closing of the readout switches to the M row selection wiring lines, the vertical shift register section including: a shift register array including M/2 shift register circuits formed of a semiconductor material containing polycrystalline silicon, and disposed for every two adjacent row selection wiring lines provided for two adjacent rows; M logic circuits for outputting the row selection control signals respectively to the M row selection wiring lines; a first binning selection wiring line for providing one-side input terminals of M/2 logic circuits connected to one of each two adjacent row selection wiring lines with a first binning control signal for selecting the one row selection wiring line; and a second binning selection wiring line for providing one-side input terminals of M/2 logic circuits connected to the other of each two adjacent row selection wiring lines with a second binning control signal for selecting the other row selection wiring line, wherein to the other-side input terminal of each of the M logic circuits, an output terminal of the shift register circuit corresponding to the row selection wiring line connected to the logic circuit is connected, each of the M logic circuits, when the first binning control signal or the second binning control signal and an output signal from the shift register circuit both have significant values, outputs the row selection control signal so as to close the readout switch, and the vertical shift register section has a normal operation mode for successively selecting the two adjacent row selection wiring lines and a binning operation mode for simultaneously selecting the two adjacent row selection wiring lines, by controlling the timings at which the first binning control signal and the second binning control signal take significant values.