发明名称 |
Adjustable over-restrictive cache locking limit for improved overall performance |
摘要 |
Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache. The cache controller is operable to determine that the first way in the cache is not lockable by the device. The cache controller is also operable to send, to the device, a rejection of the first request. The cache controller is further operable to receive a second request from the device to lock a second way in the cache. The cache controller is operable to lock the second way in the cache in response to the second request. |
申请公布号 |
US9396120(B2) |
申请公布日期 |
2016.07.19 |
申请号 |
US201414580570 |
申请日期 |
2014.12.23 |
申请人 |
INTEL CORPORATION |
发明人 |
Greenspan Daniel;Majumder Supratik |
分类号 |
G06F12/00;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
Lowenstein Sandler LLP |
代理人 |
Lowenstein Sandler LLP |
主权项 |
1. An integrated circuit comprising a cache controller, the cache controller to:
receive a first request from a device to lock a first address that corresponds to a first way in a cache; determine that the first way in the cache is not lockable for the device; send, to the device, a rejection of the first request; receive a second request from the device to lock a second address that corresponds to a second way in a cache; and lock the second way in the cache in response to the second request. |
地址 |
Santa Clara CA US |