High bandwidth amplifier

摘要

An amplifier (100) comprising:
first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal;a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10);a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10);a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3);a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); anda first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).

主权项

1. An amplifier, comprising:
a first transistor, a second transistor, a third transistor, and a fourth transistor; an input for an input signal, and a first output for a first amplified signal; a first terminal of the first transistor coupled to a first voltage rail, a second terminal of the first transistor coupled to a first terminal of the third transistor, and a gate of the first transistor coupled to the input; a first terminal of the second transistor coupled to a second voltage rail, a second terminal of the second transistor coupled to the first output, and a gate of the second transistor coupled to the input; a load coupled between a second terminal of the third transistor and a third voltage rail, and a gate of the third transistor coupled to a bias node for applying a bias voltage to the gate of the third transistor; a first terminal of the fourth transistor coupled to the first output, a second terminal of the fourth transistor coupled to a fourth voltage rail, and a gate of the fourth transistor coupled to the second terminal of the third transistor; and a first capacitive element coupled between the second terminal of the third transistor and the first output.