Integrated clock gater (ICG) using clock cascode complimentary switch logic

摘要

Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

主权项

1. A complimentary voltage switched integrated clock gater (CICG) circuit, comprising:
a first node configured to pre-charge to a first voltage level in response to a first level of a clock signal and a first level of an enable signal; a second node configured to pre-charge to the first voltage level in response to the first level of the clock signal and the first level of the enable signal; a first latch coupled to the first node, the first latch being configured to latch the first node to a second voltage level in response to a second level of the clock signal and a second level of the enable signal if the enable signal transitions to the second level before or at substantially a same time that the clock signal transitions from the first level to the second level; and a second latch coupled to the second node, the second latch being configured to latch the second node to the first voltage level in response to the second level of the clock signal and the second level of the enable signal if the enable signal transitions to the second level before or at substantially the same time that the clock signal transitions from the first level to the second level.