BUMPLESS BUILD-UP LAYER PACKAGE WITH PRE-STACKED MICROELECTRONIC DEVICES

摘要

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

主权项

1. A microelectronic package, comprising:
a bumpless build-up layer (BBUL) substrate; a plurality of stacked dies above the BBUL substrate, the plurality of stacked dies having an bottommost die proximate the BBUL substrate, and a next bottommost die above the bottommost die, wherein the bottommost die has a plurality of front side lands facing the BBUL substrate and a plurality of backside lands facing the next bottommost die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost die, wherein the next bottommost die has a plurality of front side lands facing the bottommost die, wherein the plurality of backside lands of the bottommost die is directly coupled to the plurality of front side lands of the next bottommost die by a solder layer, and wherein the front side lands of the bottommost die electrically couples the bottommost die to the BBUL substrate; an underfill material layer between the bottommost die and the next bottommost die; and an encapsulation material over the BBUL substrate and laterally adjacent to the bottommost die, the next bottommost die and the underfill material layer, wherein the encapsulation material is separate and distinct from the underfill material layer.