| 发明名称 | Data processor | ||
| 摘要 | A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers. | ||
| 申请公布号 | US9459870(B2) | 申请公布日期 | 2016.10.04 |
| 申请号 | US201414499334 | 申请日期 | 2014.09.29 |
| 申请人 | FUJITSU LIMITED | 发明人 | Otomo Toshiya;Yamashita Koichiro;Suzuki Takahisa;Yamauchi Hiromasa;Kurihara Koji;Teranishi Yuta |
| 分类号 | G06F9/30;G06F9/34;G06F15/167 | 主分类号 | G06F9/30 |
| 代理机构 | Fujitsu Patent Center | 代理人 | Fujitsu Patent Center |
| 主权项 | 1. A data processor, comprising: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers. | ||
| 地址 | Kawasaki JP | ||