| 摘要 |
<p>PURPOSE:To reduce readily a clock skew irrespective of types of LSIs by a method wherein clock signals generated based on external clock signals are respectively supplied to a plurality of circuit blocks via a first buffer, a clock supply interconnection, a loop interconnection and a plurality of branch interconnections. CONSTITUTION:A first buffer 10 is connected with a loop interconnection 11 via a clock supply interconnection 10a. Clock signals generated based on external clock signals are respectively supplied to a plurality of circuit blocks 14, 15 via the loop wire 11 and a plurality of branch interconnections 12, 13 for adjusting each of interconnection lengths in order to control a delay value. Thus, it is possible to readily reduce a clock skew irrespective of types of LSIs and also reduce variations of the clock skew due to variations of circuit constant.</p> |
