| 摘要 |
<p>A test structure is a RAM-like array of scan-clock word lines (60) which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines (60) and the rows of macrocells are scan-data bit lines (90, 92). Each testable macrocell (74) has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors (34, 44). The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. Reading causes a small voltage difference to be generated on the scan-data bit lines which is sensed by a sense amplifier. Two n-channel transistors (34, 44) are added to a macrocell (74) to make the macrocell (74) testable.</p> |
