发明名称 |
Test method of chips in a semiconductor wafer employing a test algorithm |
摘要 |
Sample chips are tested after determining the chip layout on a semiconductor wafer so that one or plural ones of untested chips are surrounded by plural ones of the sample chips that adjoin the untested samples. A good/defective judgment on the untested chips is performed by using predicted good/defective judgment results that are statistically predicted based on results of the sample test and stored statistical data of a defect generation profile including address information that indicates defective chip locations. As a result, the good/defective judgment can be performed with high accuracy even in a case where defective chips are localized in a particular region on the wafer in a concentrated manner.
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申请公布号 |
US6151695(A) |
申请公布日期 |
2000.11.21 |
申请号 |
US19980126736 |
申请日期 |
1998.07.31 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KAMO, YOSHITAKA;TOSA, HIROAKI;HIGASHI, TATSUSHI;KURODA, AKIHIRO |
分类号 |
H01L21/66;G01R31/28;G11C29/44;(IPC1-7):G01R31/28 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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