Thin film transistor and method for manufacturing thin film transistor

摘要

A thin film transistor is disclosed. The drain and source electrode layer of the thin film transistor is disposed on the substrate, in which the drain and source electrode layer is divided into a drain region and a source region. The semiconductor layer and the first insulating layer are disposed on the drain and source electrode layer, in which the first insulating layer has an upper limit of thickness. The second insulating layer is disposed on the semiconductor layer and the first insulating layer, in which the second insulating layer has a lower limit of thickness. The gate electrode layer is disposed on the second insulating layer. The passivation layer is disposed on the gate electrode layer, and the pixel electrode layer is disposed on the passivation layer.

主权项

1. A thin film transistor, comprising:
a drain and source electrode layer disposed on a substrate, wherein the drain and source electrode layer is divided into a drain region and a source region; a semiconductor layer and a first insulating layer disposed on the drain and source electrode layer, wherein the semiconductor layer has a first recess, and the first insulating layer is conformally disposed on the semiconductor layer, and the first insulating layer has a second recess; a second insulating layer disposed on the semiconductor layer and the first insulating layer, wherein a part of the second recess of the first insulating layer is overlapped by a part of the second insulating layer, wherein the second insulating layer has an opening exposing a portion of the first insulating layer; a gate electrode layer formed in the opening of the second insulating layer and in contact with the exposed portion of the first insulating layer, wherein the gate electrode layer covers the opening of the second insulating layer, and extends from a bottom of the opening along a sidewall of the opening to a top surface of the second insulating layer, and a portion of the second insulating layer is sandwiched between the gate electrode layer and the first insulating layer; a passivation layer disposed on the gate electrode layer; and a pixel electrode layer disposed on the passivation layer, wherein the permittivity of the second insulating layer is smaller than the permittivity of the first insulating layer, and a thickness of the first insulating layer is smaller than a thickness of the second insulating layer, wherein the second recess is filled by the second insulation layer and the gate electrode layer, and the gate electrode directly contacts the first insulating layer.