METHODS FOR MINIMIZING LAYOUT AREA OF IC

摘要

A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.

主权项

1. A method for minimizing a layout area of an integrated circuit, comprising:
obtaining and displaying an initial floor plan of the integrated circuit, wherein the initial floor plan comprises a plurality of partitions and a plurality of channels; obtaining a plurality of first tiles of the initial floor plan according to the partitions and the channels, wherein each of the first tiles between the partition and the channel has a fixed tile property being the partition or the channel; obtaining a plurality of second tiles around a plurality of edges between at least one of the partitions and at least one of the channels, wherein each of the second tiles has a changeable tile property which can be changed between the at least one partition and the at least one channel; obtaining a specific area path of the layout area according to the partitions, the channels and a plurality of routing densities corresponding to the channels; and changing the changeable tile properties of the second tiles according to the specific area path, to re-shape the partitions and re-route a plurality of nets within the channels.