1T-1R architecture for resistive random access memory

摘要

A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

主权项

1. A method of operating an array of memory cells, comprising:
applying a selected source line voltage to a selected source line corresponding to a selected memory cell that is selected for an operation; applying an unselected source line voltage that is different from the selected source line voltage to unselected source lines corresponding to unselected memory cells that are not selected for the operation; applying a selected word line voltage to a selected word line corresponding to the selected memory cell; and forming or setting the selected memory cell in response to applying the selected word line voltage to the selected word line; wherein each memory cell includes a resistive memory element electrically coupled in series to a corresponding transistor having a gate coupled to receive a corresponding one of a plurality of word lines and a source coupled to receive a corresponding one of a plurality of source lines.