Method of minimizing the operating voltage of an SRAM cell

摘要

An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

主权项

1. An integrated SRAM memory cell, comprising:
a silicon on insulator substrate including a semiconductor layer, an insulating layer and a semiconductor support; an n-channel transistor having source, channel and drain regions formed in said semiconductor layer; a p-channel transistor having source, channel and drain regions for in said semiconductor layer; a doped well region in said semiconductor support located under said n- and p-channel transistors; and a circuit configured to apply a variable bias voltage to said doped well region, wherein said circuit is configured to:
carry out measurements representative of a threshold voltage of the n-channel transistor and of a threshold voltage of the p-channel transistor; andadjust the variable bias voltage so that the threshold voltages of the n-channel transistor and of the p-channel transistor are substantially equal to n and p target threshold voltages, respectively.