Flash memory control method, controller and electronic apparatus

摘要

A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.

主权项

1. A memory control method for controlling a flash memory, the flash memory comprising a first memory component and a second memory component, the second memory component comprising a plurality of blocks, each block comprising a plurality of data pages, the memory control method comprising:
writing original data to the first memory component; reading from the first memory component to obtain input data, the input data comprising a plurality of input data rows; dividing the plurality of input data rows into a plurality of data groups; writing each of the input data row corresponding to each of the data groups into one of the data pages in the second memory component; writing a parity row corresponding to each of the data groups to one corresponding data page that is distinct from a data page storing the written input data row in the second memory component, wherein a number of the input data rows corresponding to each of the data groups is smaller than a number of the data pages for each of the blocks; and updating the parity row of corresponding data group according to accumulated calculation of content of the input data row each time before writing an input data row to the second memory component.