| 摘要 |
The embodiments of the present invention provide a driving circuit and a driving method, a GOA unit, a GOA circuit and a display device, to improve the response speed of the circuit and reduce the leakage current. This driving circuit comprises: at least one pull-up/pull-down unit each configured to pull up or pull down a voltage of a controlled node; each pull-up/pull-down unit comprises at least one double-gate transistor, the double-gate transistor is used to accelerate the charge or discharge of the node when being turned on, or is used to reduce the leakage current passing the node when being turned off. The embodiments of the present invention are suitable to be applied to the display production. |
| 主权项 |
1. A Gate Driver on Array (GOA), comprising at least one driving circuit each comprising a first pull-up/pull-down unit, a second pull-up/pull-down unit, a third pull-up/pull-down unit, a fourth pull-up/pull-down unit and a fifth pull-up-pull-down unit each being configured to pull up or pull down a voltage of a controlled node, wherein,
the first pull-up/pull-down unit comprises:
a first transistor, a source of the first transistor being connected with a signal input end, a first gate of the first transistor being connected with the signal input end, and a drain of the first transistor being connected with a first node; anda second transistor, a source of the second transistor being connected with the first node, a drain of the second transistor being connected with a second voltage end, and a first gate of the second transistor being connected with a second node or a fourth node; the second pull-up/pull-down unit comprises:
a third transistor, a source of the third transistor being connected with a first voltage end, a drain of the third transistor being connected with the second node, and a first gate of the third transistor being connected with a second clock signal end; anda fourth transistor, a source of the fourth transistor being connected with the second node, a drain of the fourth transistor being connected with the second voltage end, and a first gate of the fourth transistor being connected with the signal input end; the third pull-up/pull-down unit comprises:
a fifth transistor, a source of the fifth transistor being connected with a third voltage end, a drain of the fifth transistor being connected with the fourth node, and a first gate of the fifth transistor being connected with the second clock signal end; anda sixth transistor, a source of the sixth transistor being connected with the fourth node, a drain of the sixth transistor being connected with a fourth voltage end, and a first gate of the sixth transistor being connected with the first node; the fourth pull-up/pull-down unit comprises:
a seventh transistor, a source of the seventh transistor being connected with the third voltage end, a first gate of the seventh transistor being connected with the third voltage end, and a drain of the seventh transistor being connected with a third node; andan eighth transistor, a source of the eighth transistor being connected with the third node, a first gate of the eighth transistor being connected with the fourth node, and a drain of the eighth transistor being connected with the fourth voltage end; and the fifth pull-up/pull-down unit comprises:
a ninth transistor, a source of the ninth transistor being connected with a first clock signal end, a first gate of the ninth transistor being connected with the first node or the third node, and a drain of the ninth transistor being connected with an output end; anda tenth transistor, a source of the tenth transistor being connected with the output end, a first gate of the tenth transistor being connected with the second node or the fourth node, and a drain of the tenth transistor being connected with the second voltage end. |
