发明名称 Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
摘要 An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address.
申请公布号 US9489204(B2) 申请公布日期 2016.11.08
申请号 US201313842835 申请日期 2013.03.15
申请人 QUALCOMM Incorporated 发明人 Tu Jiajin;Venkumahanti Suresh K.;Mestan Brian R.
分类号 G06F9/38;G06F9/32 主分类号 G06F9/38
代理机构 Withrow & Terranova, PLLC 代理人 Withrow & Terranova, PLLC
主权项 1. A method of storing a partial target address in an instruction cache, comprising: receiving a branch instruction from an instruction cache; predicting a direction of the branch instruction as being not taken; calculating a destination address based on executing the branch instruction; determining a partial target address using the destination address; and in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in the branch instruction in the instruction cache with the partial target address.
地址 San Diego CA US