| 发明名称 |
METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE NON-VOLATILE MEMORY |
| 摘要 |
Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation. |
| 申请公布号 |
US2016379715(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201514752817 |
申请日期 |
2015.06.26 |
| 申请人 |
INTEL CORPORATION |
发明人 |
PELSTER David J.;WAKCHAURE Yogesh B.;GUO Xin;RUBY Paul D.;DAYACAP Justin R.;DOLLER Joseph F.;FRICKEY Robert E. |
| 分类号 |
G11C16/16;G11C16/34;G11C16/26 |
主分类号 |
G11C16/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a non-volatile memory; and memory control logic to:
generate a command to perform a portion of a block erase operation with respect to the block in the non-volatile memory for a block erase operation for the block;perform at least one read or write operation after executing the command; andgenerate an additional instance of the command to perform an additional portion of the block erase operation with respect to the block in response to determining that the block erase operation of the block did not complete after performing the at least one read or write operation. |
| 地址 |
Santa Clara CA US |
