Method and structure for testing embedded flash memory

摘要

A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.