发明名称 Semiconductor IC and testing method thereof
摘要 According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.
申请公布号 US2008098267(A1) 申请公布日期 2008.04.24
申请号 US20070819598 申请日期 2007.06.28
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 MIYAKE NAOMI;NAKATA YOSHIROU
分类号 G01R31/28 主分类号 G01R31/28
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