发明名称 |
Absorbing excess under-fill flow with a solder trench |
摘要 |
One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication. |
申请公布号 |
US9368422(B2) |
申请公布日期 |
2016.06.14 |
申请号 |
US201213722603 |
申请日期 |
2012.12.20 |
申请人 |
NVIDIA Corporation |
发明人 |
Zhang Leilei;Boja Ron;Yee Abraham F.;Bokharey Zuhair |
分类号 |
H01L23/12;H01L23/48;H01L29/40;H01L23/31;H01L23/00;H01L21/56 |
主分类号 |
H01L23/12 |
代理机构 |
Artegis Law Group, LLP |
代理人 |
Artegis Law Group, LLP |
主权项 |
1. An integrated circuit package, comprising:
a substrate; one or more devices mounted on the substrate; one or more electrical connections disposed between the substrate and the one or more devices; a layer of under-fill configured to secure the one or more devices on the substrate; and a solder trench formed in the substrate, wherein the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication, and wherein the solder trench is comprised of a plurality of cylindrical apertures formed in the substrate, wherein the cylindrical apertures are arranged in a staggered pattern relative to one another. |
地址 |
Santa Clara CA US |