发明名称 Determining a set of timing paths for creating a circuit abstraction
摘要 Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical timing paths in the circuit design whose delay is affected by a change in an input capacitance of a circuit element in the set of circuit elements. The embodiment can then identify a set of side loads based on the set of timing paths, and can create the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during optimization of the circuit element.
申请公布号 US9390222(B2) 申请公布日期 2016.07.12
申请号 US201414508523 申请日期 2014.10.07
申请人 SYNOPSYS, INC. 发明人 Segal Russell;Zou Peiqing
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Park, Vaughan, Fleming & Dowler LLP 代理人 Park, Vaughan, Fleming & Dowler LLP ;Sahasrabuddhe Laxman
主权项 1. In an electronic design automation (EDA) tool in a computer, a method for determining a set of timing paths for creating a circuit abstraction, the method comprising: receiving, by the EDA tool in the computer, a circuit element in the circuit design that is a candidate for optimization; identifying, by the EDA tool in the computer, critical timing paths in the circuit design whose delay is affected by a change in an input capacitance of the circuit element, wherein said identifying includes identifying at least one critical timing path that does not pass through the circuit element, but whose delay is affected by a change in an input capacitance of the circuit element; and creating, by the EDA tool in the computer, a circuit abstraction based at least on the identified critical timing paths.
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