Asynchronous successive approximation register analog-to-digital converter and internal clock generator included therein

摘要

An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.

主权项

1. An internal clock generator in an SAR ADC comprising:
a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse, wherein the delay block includes: a delay controller configured to increase or decrease the bias voltage according to the up pulse or the down pulse; and an inverter chain configured to increase or decrease the delay time according to increasing or decreasing of the bias voltage.