Heterojunction semiconductor device for reducing parasitic capacitance

摘要

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

主权项

1. A semiconductor device, comprising:
an active layer made of III-V group semiconductors; at least one source electrode disposed on the active layer; at least one drain electrode disposed on the active layer; at least one gate electrode disposed on or above the active layer and between the source electrode and the drain electrode; an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode, the interlayer dielectric having at least one first inter-source via hole, at least one first inter-drain via hole, and at least one inter-gate via hole; at least one inter-source layer disposed on the interlayer dielectric; at least one inter-source plug filled in the first inter-source via hole and electrically connected to the source electrode and the inter-source layer; at least one inter-drain layer disposed on the interlayer dielectric; at least one inter-drain plug filled in the first inter-drain via hole and electrically connected to the drain electrode and the inter-drain layer; at least one inter-gate layer disposed on the interlayer dielectric and above the gate electrode; at least one inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer; a first insulating layer covering the inter-source layer, the inter-gate layer, and the inter-drain layer, the first insulating layer having at least one source via hole and at least one drain via hole therein; a first source pad disposed on the first insulating layer; a first drain pad disposed on the first insulating layer; at least one source plug filled in the source via hole and electrically connected to the first source pad and the inter-source layer; at least one drain plug filled in the drain via hole and electrically connected to the first drain pad and the inter-drain layer; a second insulating layer disposed on the first source pad, the first drain pad, and the first insulating layer, wherein the second insulating layer has a source pad opening and a drain pad opening to respectively expose a portion of the first source pad and a portion of the first drain pad, and the second insulating layer has a thickness greater than 7 μm; a second source pad disposed on the second insulating layer; a second drain pad separated from the second source pad and disposed on the second insulating layer; a source pad connection portion disposed in the source pad opening and electrically connected to the first source pad and the second source pad; and a drain pad connection portion disposed in the drain pad opening and electrically connected to the first drain pad and the second drain pad.