| 摘要 |
A voltage monitor circuit comprises a monitored voltage input 42, a reference capacitor 32 arranged to be able to store a value of the monitored voltage as a reference capacitor voltage and a timeout capacitor 34 arranged to be able to store a value of the monitored voltage as a timeout capacitor voltage. The timeout capacitor undergoes a higher leakage than the reference capacitor. The voltage monitor circuit also comprises a comparator 2 arranged to compare the monitored voltage to the reference capacitor voltage; compare the timeout capacitor voltage to the reference capacitor voltage; and produce a logic signal on an output 9 of the comparator based on the comparisons, the logic signal having a first logic value at least if the reference capacitor voltage is lower than or equal to both the monitored voltage and the timeout capacitor voltage. |
