发明名称 |
Floating point processor with high speed rounding circuit |
摘要 |
In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data derived is detected from the derived overflow signals.
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申请公布号 |
US5495434(A) |
申请公布日期 |
1996.02.27 |
申请号 |
US19940337017 |
申请日期 |
1994.11.07 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TANIGUCHI, TAKASHI |
分类号 |
G06F7/38;G06F7/00;G06F7/485;G06F7/508;G06F7/544;G06F7/57;G06F7/76;(IPC1-7):G06F7/50;G06F7/02 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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