DIGITAL CLOCK SIGNAL GENERATION APPARATUS AND METHOD REGARDLESS OF INPUT SIGNAL DUTY RATE

摘要

An apparatus and a method of generating a digital clock signal irrespective of input signal duty rate is provided to reduce power consumption of a microprocessor which is driven at high speed at low voltage. A clock signal delay unit(200) delays a clock signal to generate plural clock signals having different phases. A digitizer(300) detects the phases of the delayed clock signals as a digital value at rising edge of flip-flop. A selection signal generating unit(400) detects clock edge, in which output signal values of the digitizer are shifted into different digital values, to generate a selection signal. A selection unit(500) selects a specific signal from the delay signals having the different phase.