| 发明名称 |
MULTIPLIER PIPELINING OPTIMIZATION WITH A BIT FOLDING CORRECTION |
| 摘要 |
One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred. |
| 申请公布号 |
US2016274866(A1) |
申请公布日期 |
2016.09.22 |
| 申请号 |
US201514664669 |
申请日期 |
2015.03.20 |
| 申请人 |
Intel Corporation |
发明人 |
O'DWYER T.J.;LAURENT PIERRE |
| 分类号 |
G06F7/533;G06F7/72 |
主分类号 |
G06F7/533 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system comprising:
a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred. |
| 地址 |
Santa Clara CA US |
