Integrated circuit package substrate

摘要

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

主权项

1. A package substrate comprising:
a first side including one or more lands, the one or more lands having a first surface finish disposed on the one or more lands; and a second side disposed opposite to the first side, the second side having die interconnect region, the die interconnect region having one or more electrical routing features embedded therein, the one or more electrical routing features having a second surface finish disposed on, and in direct contact with, the one or more electrical routing features, wherein the electrical routing features are configured to bond with die interconnect structures of one or more dies and the second surface finish has a different chemical composition than the first surface finish.