Method for synchronizing independent clock signals

摘要

An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

主权项

1. An apparatus, comprising:
a selection unit configured to select a first clock signal or a second clock signal to generate an output clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; and circuitry coupled to the selection unit, wherein the circuitry is configured to:
send a first value of a control signal to the selection unit, wherein the first value causes the selection unit to select the first clock signal;send a second value of the control signal to the selection unit, wherein the second value causes the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal, wherein the subset of clock pulses of the second clock signal includes a given clock pulse, wherein the given clock pulse is selected responsive to a detection of a given transition of the first clock signal, wherein the subset of clock pulses of the second clock signal includes at least one additional clock pulse of the second clock signal, and wherein the at least one additional clock pulse of the second clock signal occurs within a clock period of the first clock signal from the occurrence of the given transition;assert a clock valid signal responsive to a determination the given clock pulse has begun; andde-assert the clock valid signal responsive to a determination the given clock pulse has ended.