| 摘要 |
.A clock driver comprises a bidirectional binary counter set in subtraction mode, having synchronous parallel loading inputs, a compute mode enable input, an input of asynchronous installation to zero state, overflow output of which forms clock driver output connected to enable input for synchronous parallel installation to state determined by configuration variables which are supplied to parallel loading inputs. There is a second counter set in subtraction mode having synchronous parallel loading inputs, a compute mode enable input, an input of asynchronous installation to zero state, two-input OR element, an invertor, a circuit comprising in series connected resistor and capacitor, inputs of asynchronous installation to zero state are connected to each other and connected to connection point of the circuit of in series connected resistor and capacitor, connected to a power source; overflow input of the second counter is connected to enable input for synchronous parallel loading and one of inputs of OR element, output of which is connected to enable input for synchronous parallel loading of the first counter; first counter overflow input is connected to compute mode enable input for the second counter, to OR element second input and to invertor input, output ot the said invertor is connected to compute mode enable input of the first counter; parallel loading inputs of the first counter serve for supplying a second configuration word, clock inputs of first and second counters are connected to each other forming input of the clock driver, to which pulses periodic sequence is supplied from input of an external clock oscillator. |
