| 摘要 |
Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host- program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor. |
