Circuits and Methods for Performance Optimization of SRAM Memory

摘要

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

主权项

1. A memory controller circuit, external to and coupled to a static random access memory (SRAM) circuit, to control read and write data accesses to the SRAM circuit by outputting a precharge control signal to the SRAM circuit, the memory controller circuit comprising:
precharge mode control circuitry to output: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur; the SRAM circuit including an array of SRAM cells arranged in rows and columns to store data, each SRAM cell coupled to a corresponding word line along a row of SRAM cells, and each SRAM cell coupled to a corresponding pair of complementary bit lines to output a differential voltage corresponding to a stored datum on the corresponding pair of complementary bit lines responsive to a row select voltage on the corresponding word line; wherein the memory controller circuit is coupled to cause a precharge circuit to precharge the corresponding pair of complementary bit lines to a precharge voltage responsive to the precharge control signal.