METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION

摘要

Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

主权项

1. An apparatus, comprising:
an encoder circuit configured to encode commands, wherein the commands are internal to a memory and are encoded based on their command type; a latency shifter circuit coupled to the encoder circuit and configured to provide a latency to the encoded commands; and a decoder circuit coupled to the latency shifter circuit and configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.