Hierarchical statistically multiplexed counters and a method thereof

摘要

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

主权项

1. A counter architecture implemented in a network device, the counter architecture comprising a plurality of levels of statistically multiplexed counters, wherein each of the levels of statistically multiplexed counters includes N counters arranged in N/P rows, wherein each of the N/P rows includes P base counters and S subcounters, wherein any of the P base counters configured to be dynamically concatenated with one or more of the S subcounters to flexibly extend the counting capacity.