发明名称 |
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME |
摘要 |
<P>PROBLEM TO BE SOLVED: To disable a chip that does not operate normally while reducing a problem resulting from a wire connected to the chip that does not operate normally. <P>SOLUTION: A layered chip package 1 comprises a body 2 including a plurality of pairs of layer portions and wires 3A and 3B arranged on the side surfaces of the body 2. The plurality of pairs of layer portions includes a specific pair of layer portions 10PS having a first type layer portion and a second type layer portion. The first-type layer portion is connected to a semiconductor chip and includes a plurality of electrodes having an end surface arranged on the side surface of the body 2 but the second type of layer portion does not. A laminated body in which two or more pairs of layer portions, the number of which is determined in advance, are stacked is manufactured using a laminated foundation structure in which two foundation structures including a plurality of arranged spare layer portions are stacked and the body 2 is manufactured by stacking the first type layer portions to be added in the same number as that of the specific pairs of layer portions included therein. <P>COPYRIGHT: (C)2010,JPO&INPIT |
申请公布号 |
JP2010183058(A) |
申请公布日期 |
2010.08.19 |
申请号 |
JP20090207679 |
申请日期 |
2009.09.09 |
申请人 |
HEADWAY TECHNOLOGIES INC;TDK CORP;SAE MAGNETICS (HK) LTD |
发明人 |
SASAKI YOSHITAKA;ITO HIROYUKI;HARADA TATSUYA;OKUZAWA NOBUYUKI;SUEKI SATORU;IKEJIMA HIROSHI |
分类号 |
H01L25/065;H01L25/07;H01L25/18 |
主分类号 |
H01L25/065 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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