| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory which realizes a reduction of a test period and an improvement in test accuracy in high operating frequency by switching an operating mode according to DMA test entries, and to provide a system LSI which incorporates the memory. SOLUTION: A memory macro (1) switches an operating mode according to the status of a mode control terminal (SEL). I/O common mode: an input selector (3) selects a first data input bus (61), and an output selector (4) selects a first data output bus (71). A column decoder (10) selects eight bit lines per address. Thus all data input/output terminals (PDQ 0-7) are utilized bidirectionally. I/O separate mode: the input selector (3) selects a second data input bus (62), and the output selector (4) selects a second data output bus (72). The column decoder (10) selects four bit lines per address. Thus half of the data input/output terminals (PDQ 0-3) are utilized for data input, and remaining half (PDQ 4-7) are utilized for data output. COPYRIGHT: (C)2005,JPO&NCIPI
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