| 摘要 |
A variable delay circuit comprises a plurality of first series-connected variable delay elements for sequentially delaying a reference clock signal or data signal; a second variable delay element connected in parallel with the plurality of first variable delay elements for delaying the reference clock signal; a phase comparator for comparing the phase of the reference clock signal as delayed by the plurality of first variable delay elements with the phase of the reference clock signal as delayed by the second variable delay element; and a delay amount control part for controlling, based on a comparison result of the phase comparator, the delay amounts of the plurality of first variable delay elements such that the phase of the reference clock signal as delayed by the plurality of first variable delay elements becomes approximately equal to the phase of the reference clock signal as delayed by the second variable delay element by a predetermined number of cycles.
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