发明名称 |
MULTI-PHASE DELAY LOCKED LOOP WITH EQUALLY-SPACED PHASES OVER A WIDE FREQUENCY RANGE AND METHOD THEREOF |
摘要 |
A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.
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申请公布号 |
US2007285138(A1) |
申请公布日期 |
2007.12.13 |
申请号 |
US20070760782 |
申请日期 |
2007.06.10 |
申请人 |
BHOWMIK PRASENJIT;KRISHNAN SUNDARARAJAN;SRIRAM G |
发明人 |
BHOWMIK PRASENJIT;KRISHNAN SUNDARARAJAN;SRIRAM G. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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