Droop reduction circuit for charge pump buck converter

摘要

A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout>a first Vout level and controls the BC to regulate to a second Vout level>the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

主权项

1. A method of power conversion, the method comprising:
using a charge pump buck converter (CPBC) that includes: a charge pump (CP) stage; a buck converter (BC) stage connected in parallel with said CP stage between an input terminal (IN) and an output terminal (OUT); control logic coupled through a switch driver to a least one control node of at least one power switch for driving an inductor of said BC stage; and control circuitry including a duty cycle or repetition rate generator block (cycle/rate generator block); wherein using said CPBC includes:
providing a first voltage level, which is coupled to said CP stage;providing a second voltage level, which is coupled to said cycle/rate generator block, said first voltage level being above said second voltage level;using said cycle/rate generator block to provide a duty cycle or repetition rate output coupled to an input of an under voltage (UV) monitor block, wherein said UV monitor block includes a UV comparator triggered by a UV threshold and is coupled between said OUT and an input of said control logic;during a power up, when a voltage at said IN (Vin) is rising with time:
applying clock signals to said CP stage to increase a voltage at said OUT (Vout);responsive to said Vout exceeding a first output voltage level (first Vout level), disabling said CP stage;responsive to said Vin exceeding an input reference voltage, controlling said BC stage to regulate said Vout at a second Vout level that is above said first Vout level;tracking said Vout using said UV monitor block; andduring a handoff between said CP stage and said BC stage during said power up, if said Vout drops below said UV threshold, using said UV monitor block to modify said input of said control logic to increase charging supplied to said inductor.