Fully valid-gated read and write for low power array

摘要

In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

主权项

1. A memory, comprising:
an array having one or more rows configured to store a data word, wherein the one or more rows each include valid-gated read circuitry configured to store data that indicates whether the data word stored in the corresponding row has a valid state and conditionally gate a read wordline path in the corresponding row according to at least the stored data; one or more output latches configured to output data read from the array; and valid-gated output latch clocking coupled to the one or more output latches and to the valid-gated read circuitry in each row, wherein the valid-gated output latch clocking includes circuitry configured to conditionally gate a read clock configured to open the one or more output latches according to at least the stored data that indicates whether the data word stored in an indexed row in the array has a valid state.