TWO-STAGE DIGITAL DOWN-CONVERSION OF RF PULSES

摘要

A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth. A stream of second stage I/Q quadrature samples has an optimal signal to noise ratio and allows accurate estimation of RF pulse parameters (magnitude, phase and frequency) by means of a second I/Q signal processor and/or by storing second I/Q data for subsequent processing and analysis.

主权项

1. A two-stage digital down-conversion system, comprising:
A. an analog to digital converter (ADC) responsive to an applied analog signal, generating a digital output signal at a digital output, wherein the digital output is represented by a succession of digital samples, representing succession of samples of the input signal; B. a first-stage digital down-conversion (DDC) module generating first-stage quadrature digital components I1 and Q1, comprising:
i. first stage digital local oscillator (LO), generating sine and cosine signals at first stage frequency;ii. first stage multipliers, generating sequence of digital data being the product of ADC samples and first stage LO sine and cosine signals;iii. first stage Low pass filters, having cutoff frequency at first-stage bandwidth of output of first stage multipliers; andiv. first stage decimators, providing first-stage down-sampling of output of first stage low pass filters; C. a first stage I/Q memory for storing first-stage quadrature data; D. a first stage I/Q processor module, performing first-stage amplitude envelope, phase and frequency detection E. a second stage DDC module, generating second-stage quadrature components I2/Q2, based on first stage I1/Q1 quadrature components, comprising:
i. A second stage digital local oscillator (LO), generating second-stage sine and cosine signals at second stage frequency f2 as cos(f2*t) and sin(f2*t);ii. an inverter, reversing the sign of sine LO component if the sign value calculated by first-stage I/Q processor is negative;iii. second stage multipliers, generating products of first-stage quadrature I1 and Q1 digital samples with second-stage sine and cosine functions;iv. adders, forming sum and difference of multiplier outputs as
I2(t)=I1(t)*cos(f2*t)−Sign*Q1(t)*sin(f2*t)Q2(t)=Sign*I1(t)*sin(f2*t)+Q1(t)*cos(f2*t)v. second stage low pass filters having a second stage bandwidth; andvi. second stage decimators, having second stage decimation rate.