| 发明名称 |
Programmable Logic Device and Logic Integration Tool |
| 摘要 |
An object of the present invention is to provide a high reliable/high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability for a failure of the configuration memory is higher than reliability in the other area. |
| 申请公布号 |
US2016241247(A1) |
申请公布日期 |
2016.08.18 |
| 申请号 |
US201315025821 |
申请日期 |
2013.09.30 |
| 申请人 |
HITACHI, LTD. |
发明人 |
KANNO Yusuke;KANEKAWA Nobuyasu;SHIMAMURA Kotaro;TOBA Tadanobu;HIROTSU Teppei;YAMADA Tsutomu |
| 分类号 |
H03K19/177;H03K19/21 |
主分类号 |
H03K19/177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A programmable logic device, comprising:
a plurality of configuration memories, wherein the configuration memories are divided into a plurality of areas and are arranged, and a part of the plurality of areas is set to a high reliable area where reliability for a failure of the configuration memory is higher than reliability in the other area. |
| 地址 |
Tokyo JP |
