发明名称 Power Switch Ramp Rate Control Using Selectable Daisy-Chained Connection of Enable to Power Switches or Daisy-Chained Flops Providing Enables
摘要 In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.
申请公布号 US2016241240(A1) 申请公布日期 2016.08.18
申请号 US201514622111 申请日期 2015.02.13
申请人 Apple Inc. 发明人 Suzuki Shingo;Krishnamurthy Harsha;Catovic Edvin;Goel Rajat;Gopalan Manoj
分类号 H03K19/003;H03K19/00 主分类号 H03K19/003
代理机构 代理人
主权项 1. A power control apparatus comprising: a plurality of power switch segments each comprising a plurality of power switches, wherein: the power switches are coupled to a first power rail that is powered to a power supply voltage during use;the power switches are coupled to one or more power supply inputs of a block of circuits; andthe power switches in a given power switch segment logically share a power switch enable input to the given power switch segment; a plurality of flops coupled in series, wherein a first flop in the series is coupled to a global power switch enable input; a plurality of multiplexors, wherein: each multiplexor includes a first input coupled to an output of a given flop of the plurality of flops and a second input coupled to a power switch enable output of one of the plurality of power switch segments; andeach multiplexor has an output coupled to the power switch enable input of a respective power switch segment of the plurality of power switch segments; and clock circuitry configured to: generate a clock for the plurality of flops; andduring a power up cycle of the block, sequence a clock frequency at which the clock toggles through a preselected plurality of frequencies, each frequency of the plurality of frequencies used for a preselected number of clock pulses at that frequency.
地址 Cupertino CA US