Semiconductor memory device and semiconductor device

摘要

For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.