| 发明名称 | Immunity to inline charging damage in circuit designs | ||
| 摘要 | Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device. | ||
| 申请公布号 | US9378329(B1) | 申请公布日期 | 2016.06.28 |
| 申请号 | US201514707576 | 申请日期 | 2015.05.08 |
| 申请人 | INTERNATIONAL BUSINESS MACHINES CORPORATION | 发明人 | Henderson Zachary;Hibbeler Jason D.;Hook Terence B.;Palmer Nicholas;Peterson Kirk D. |
| 分类号 | G06F17/50;H01L23/535;H01L29/78 | 主分类号 | G06F17/50 |
| 代理机构 | Roberts Mlotkowski Safran & Cole, P.C. | 代理人 | Meyers Steven J.;Roberts Mlotkowski Safran & Cole, P.C. |
| 主权项 | 1. A method of checking a design of an integrated circuit using an antenna rule, comprising: determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor; comparing the determined figure of merit to a limit; and deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit, wherein the determining and the comparing are performed by a computer device, and further comprising manufacturing a semiconductor structure based on the design of the integrated circuit. | ||
| 地址 | Armonk NY US | ||